With the use of wire-bonding or TAB (Tape Automated Bonding) technology, Conventional semiconductor packages, particularly the semiconductor packages each including at least two chips, suffer problems such as too long trace, connection of two lead frames, complicated material preparation and packaging processes, as well as the quality defects incurred in molding due to the weaker mechanical strength of TAB.
With semiconductor packages tending to be light and thin while chips gradually becomes larger in size to meet more sophisticated function demand, various schemes have been suggested for packaging a chip or more than a chip in such ways that the completed package as a whole can be smaller, particularly can be lighter and thinner. One among the various schemes is the prior art disclosed in U.S. Pat. No. 5,331,235 and represented by FIG. 1, which suggested a semiconductor package including at least two semiconductor chips 32 and 34 respectively having bumps 33 and 35 thereof facing each other and being connected to a lead frame 37 through tapes 31, wherein a solder 36 is interposed between the two semiconductor chips; which also suggested another scheme as shown in FIG. 2 where a semiconductor package C includes at least two semiconductor chips 32 and 34 respectively having bumps 33 and 35 thereof facing each other, and being connected to tapes 31 that are connected to lead frame 37 partly inserted between the two semiconductor chips 32 and 34.
Although various schemes other than the above two were also suggested by the same prior art, they are all characterized by using tapes for electrical connection between bare chips and lead frames, thereby still suffer problems similar to those suffered by conventional semiconductor packaging, resulting in the need of developing a new scheme to keep pace with the trend of demanding renovated multi-chip semiconductor packages, leading to the suggestion of the present invention.